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CY7C0851V/CY7C0852V/CY7C0853V PRELIMINARY CY7C0831V/CY7C0832V
3.3V 64K/128K/256K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM
Features (all)
* True dual-ported memory cells that allow simultaneous access of the same memory location * Synchronous pipelined * Organization of 2M, 4.5M, and 9M devices -- 256K x 36 (CY7C0853V) -- 128K x 36 (CY7C0852V) -- 64K x 36 (CY7C0851V) -- 256K x 18 (CY7C0832V) * * * * -- 128K x 18 (CY7C0831V) Pipelined output mode allows fast 150-MHz operation 0.18-micron CMOS for optimum speed and power High-speed clock to data access: 4.0 ns (max.) 3.3V low operating power -- Active = 300 mA (typical) -- Standby = 10 mA (typical) Interrupt flags for message passing Global master reset Separate byte enables on both ports Commercial and industrial temperature ranges IEEE 1149.1-compatible JTAG boundary scan 172-ball BGA (1 mm pitch) (15 mm x 15 mm) 120-pin TQFP (14 mm x 14 mm x 1.4 mm) 176-pin TQFP (24 mm x 24 mm x 1.4 mm) FLEx36 devices are pin footprint upgradeable from 2M to 4M to 9M Functional Description (all) The CY7C085XV/CY7C083XV are 2M, 4.5M, and 9M pipelined, synchronous, true dual-port static RAMs that are high-speed, low-power 3.3V CMOS. Two ports are provided, permitting independent, simultaneous access for Reads from any location in memory. A particular port can write to a certain location while another port is reading that location. The result of writing to the same location by more than one port at the same time is undefined. Registers on control, address, and data lines allow for minimal set-up and hold time. Functional Description (all except CY7C0853V) During a Read operation, data is registered for decreased cycle time. Clock to data valid tCD2 = 4.0 ns at 150 MHz. Each port contains a burst counter on the input address register. After externally loading the counter with the initial address, the counter will increment the address internally (more details to follow). The internal Write pulse width is independent of the duration of the R/W input signal. The internal Write pulse is self-timed to allow the shortest possible cycle times. A HIGH on CE0 or LOW on CE1 for one clock cycle will power down the internal circuitry to reduce the static power consumption. One cycle with chip enables asserted is required to reactivate the outputs. Counter enable (CNTEN) inputs are provided to stall the operation of the address input and utilize the internal address generated by the internal counter for fast, interleaved memory applications. A port's burst counter is loaded when the port's address strobe (ADS) and CNTEN signals are LOW. When the port's CNTEN is asserted and the ADS is deasserted, the address counter will increment on each LOW to HIGH transition of that port's clock signal. This will Read/Write one word from/into each successive address location until CNTEN is deasserted. The counter can address the entire memory array, and will loop back to the start. Counter reset (CNTRST) is used to reset the unmasked portion of the burst counter to 0s. A counter-mask register is used to control the counter wrap. The counter and mask register operations are described in more detail in the following sections. New features added to the CY7C08X1V/CY7C08X2V devices include: readback of burst-counter internal address value on address lines, counter-mask registers to control the counter wrap-around, counter interrupt (CNTINT) flags, readback of mask register value on address lines, retransmit functionality, interrupt flags for message passing, JTAG for boundary scan, and asynchronous Master Reset (MRST).
* * * * * * * * *
Features (all except CY7C0853V)
* Counter wrap around control -- Internal mask register controls counter wrap-around -- Counter-interrupt flags to indicate wrap-around -- Memory block retransmit operation * Counter readback on address lines * Mask register readback on address lines * Dual Chip Enables on both ports for easy depth expansion
Cypress Semiconductor Corporation Document #: 38-06059 Rev. *C
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 Revised April 22, 2002
CY7C0851V/CY7C0852V/CY7C0853V PRELIMINARY
Logic Block Diagram[1]
OEL R/WL B0L B1L B2L B3L CE0L [2] CE1L OER R/W R B0R B1R B2R B3R
CY7C0831V/CY7C0832V
[2]
CE0R [2] CE1R
[2]
DQ27L-DQ35L DQ18L-DQ26L DQ9L-DQ17L DQ0L-DQ8L
9 9 9 9
9 9
DQ27R-DQ35R DQ18R-DQ26R DQ9R-DQ17R DQ0R-DQ8R
I/O Control
I/O Control
9 9
Addr. Read Back
True Dual-Ported RAM Array
Addr. Read Back
A0L-A16L CNT/MSKL[2] ADSL[2] CNTENL[2] CNTRSTL[2] CLKL[2] CNTINTL[2]
17
17
Mask Register Counter/ Address Register Mirror Reg TMS TDI TCK
Mask Register Counter/ Address Register Mirror Reg
A0R-A16R CNT/MSKR[2] ADSR[2] CNTENR[2] CNTRSTR[2] CLKR[2] CNTINTR[2]
Address Decode
Address Decode
Interrupt
INTL
MRST
Reset Logic
JTAG
TDO
Interrupt Logic
Logic
INTR
Notes: 1. CY7C0851V has 16 address bits instead of 17. CY7C0832V and CY7C0853V have 18 address bits instead of 17. CY7C083XV does not have B2 and B3 inputs. CY7C083XV does not have DQ18-DQ35 data bits. JTAG not implemented on CY7C083XV. 2. This feature is not available on the CY7C0853V.
Document #: 38-06059 Rev. *C
Page 2 of 33
CY7C0851V/CY7C0852V/CY7C0853V PRELIMINARY
Pin Configurations
172-ball BGA Top View
CY7C0831V/CY7C0832V
1
DQ32L
2
DQ30L
3
CNTINTL
4
VSSQ
5
DQ13L
6
VDDQ
7
DQ11L
8
DQ11R
9
VDDQ
10
DQ13R
11
VSSQ
12
CNTINTR
13
DQ30R
14
DQ32R
A
A0L DQ33L DQ29L DQ17L DQ14L DQ12L DQ9L DQ9R DQ12R DQ14R DQ17R DQ29R DQ33R A0R
B
NC A1L DQ31L DQ27L INTL DQ15L DQ10L DQ10R DQ15R INTR DQ27R DQ31R A1R NC
C
A2L A3L DQ35L DQ34L DQ28L DQ16L VSSQ VSSQ DQ16R DQ28R DQ34R DQ35R A3R A2R
D
A4L A5L CE1L B0L VDDQ VSSA VDDA VDDQ B0R CE1R A5R A4R
E
VDD A6L A7L B1L VDDA VSSA B1R A7R A6R VDD
F
OEL B2L B3L CE0L
G
VSS R/WL A8L CLKL
CY7C0851V CY7C0852V
VSSA VDDA
CE0R
B3R
B2R
OER
CLKR
A8R
R/WR
VSS
H
A9L A10L VSS ADSL ADSR MRST A10R A9R
J
A11L A12L A15L CNTRSTL VDDQ VDDA VSSA VDDQ CNTRSTR A15R A12R A11R
K
CNT/MSKL A13L CNTENL DQ26L DQ25L DQ19L VSSQ VSSQ DQ19R DQ25R DQ26R CNTENR A13R CNT/MSKR
L
A16L[3] A14L DQ22L DQ18L TDI DQ7L DQ2L DQ2R DQ7R TCK DQ18R DQ22R A14R A16R[3]
M
DQ24L DQ20L DQ8L DQ6L DQ5L DQ3L DQ0L DQ0R DQ3R DQ5R DQ6R DQ8R DQ20R DQ24R
N
DQ23L DQ21L TDO VSSQ DQ4L VDDQ DQ1L DQ1R VDDQ DQ4R VSSQ TMS DQ21R DQ23R
P
Note: 3. For CY7C0851V, pins M1 and M14 are NC.
Document #: 38-06059 Rev. *C
Page 3 of 33
CY7C0851V/CY7C0852V/CY7C0853V PRELIMINARY
Pin Configurations (continued)
172-ball BGA Top View 1
DQ32L
CY7C0831V/CY7C0832V
2
DQ30L
3
NC
4
VSSQ
5
DQ13L
6
VDDQ
7
DQ11L
8
DQ11R
9
VDDQ
10
DQ13R
11
VSSQ
12
NC
13
DQ30R
14
DQ32R
A
A0L DQ33L DQ29L DQ17L DQ14L DQ12L DQ9L DQ9R DQ12R DQ14R DQ17R DQ29R DQ33R A0R
B
A17L A1L DQ31L DQ27L INTL DQ15L DQ10L DQ10R DQ15R INTR DQ27R DQ31R A1R A17R
C
A2L A3L DQ35L DQ34L DQ28L DQ16L VSSQ VSSQ DQ16R DQ28R DQ34R DQ35R A3R A2R
D
A4L A5L VDD B0L VDDQ VSSA VDDA VDDQ B0R VDD A5R A4R
E
VDD A6L A7L B1L VDDA VSSA B1R A7R A6R VDD
F
OEL B2L B3L VSS
CY7C0853V
VSS
B3R
B2R
OER
G
VSS R/WL A8L CLKL CLKR A8R R/WR VSS
H
A9L A10L VSS VSS VSSA VDDA VSS MRST A10R A9R
J
A11L A12L A15L VDD VDDQ VDDA VSSA VDDQ VDD A15R A12R A11R
K
VDD A13L VSS DQ26L DQ25L DQ19L VSSQ VSSQ DQ19R DQ25R DQ26R VSS A13R VDD
L
A16L A14L DQ22L DQ18L TDI DQ7L DQ2L DQ2R DQ7R TCK DQ18R DQ22R A14R A16R
M
DQ24L DQ20L DQ8L DQ6L DQ5L DQ3L DQ0L DQ0R DQ3R DQ5R DQ6R DQ8R DQ20R DQ24R
N
DQ23L DQ21L TDO VSSQ DQ4L VDDQ DQ1L DQ1R VDDQ DQ4R VSSQ TMS DQ21R DQ23R
P
Document #: 38-06059 Rev. *C
Page 4 of 33
CY7C0851V/CY7C0852V/CY7C0853V PRELIMINARY
Pin Configurations (continued)
176-pin Thin Quad Flat Pack (TQFP) Top View
DQ11R DQ12R DQ17R DQ15R DQ10R VSS DQ13R DQ14R DQ16R DQ15L DQ17L DQ13L VSS DQ16L DQ14L DQ12L DQ11L DQ10L DQ9L DQ9R VDD VDD
CY7C0831V/CY7C0832V
CNTINTR INTR
INTL CNTINTL
DQ29R DQ28R
DQ27R
DQ30R
174 173
171 170
168 167
165 164
162 161
159 158
156 155
153 152
150 149
145 144
142 141
139 138
136 135 134
DQ31R
DQ31L
DQ30L
DQ27L
176 175
148 147
172
169
166
163
160
157
154
151
146
143
140
137
133
DQ32R DQ33R
DQ33L DQ32L
DQ28L DQ29L
VDD VSS
VSS VDD
DQ34L DQ35L NC A0L A1L A2L A3L VSS VDD A4L A5L A6L A7L B0L B1L CE1L B2L B3L OE L CE0L VDD VDD VSS VSS R/WL CLK L VSS ADSL CNTENL CNTRSTL CNT/MSKL A8L A9L A10L A11L A12L VSS VDD A13L A14L A15L A16L DQ24L DQ20L
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115
DQ34R DQ35R NC A0R A1R A2R A3R VSS VDD A4R A5R A6R A7R B0R B1R CE1R B2R B3R OER CE0R VDD VDD VSS VSS R/WR CLKR MRST ADSR CNTENR CNTRSTR CNT/MSKR A8R A9R A10R A11R A12R VSS VDD A13R A14R A15R A16R DQ24R DQ20R
CY7C0851V CY7C0852V
114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89
45 46
73 74
81
75
64
55
49
52
58
61
70
67
78
DQ19R DQ25R
84
DQ18R
DQ21R
DQ8L
Document #: 38-06059 Rev. *C
DQ22R
DQ22L
DQ21L
DQ18L
DQ1R
DQ5R
DQ8R
DQ5L
DQ1L
TMS TCK
TDI TDO
VDD
VDD
DQ23R DQ26R
DQ26L DQ23L
DQ25L DQ19L
DQ2R DQ3R
DQ6R DQ7R
DQ0L DQ0R
VSS DQ4R
DQ7L DQ6L
DQ4L VSS
DQ3L DQ2L
VDD VSS
VSS VDD
85 86 87
79 80
71 72
62 63
53 54
47 48
50 51
56 57
59 60
65 66
68 69
76 77
82 83
88
Page 5 of 33
CY7C0851V/CY7C0852V/CY7C0853V PRELIMINARY
Pin Configurations (continued)
120-pin Thin Quad Flat Pack (TQFP)[4] Top View
DQ15L DQ14L DQ13L VDD VSS DQ12L DQ11L DQ10L DQ9L INTL CNTINTL CNTINTR A1L A0L DQ17L DQ16L DQ12R VSS VDD DQ13R DQ14R DQ15R DQ16R DQ17R A0R A1R 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 INTR DQ9R DQ10R DQ11R
CY7C0831V/CY7C0832V
A2L A3L VSS VDD A4L A5L A6L A7L CE1L B0L B1L OEL CE0L VDD VSS R/WL CLKL VSS ADSL CNTENL CNTRSTL CNT/MSKL A8L A9L A10L A11L A12L VSS VDD A13L
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91
CY7C0831V CY7C0832V
A2R A3R VSS VDD A4R A5R A6R A7R CE1R B0R B1R OER CE0R VDD VSS R/WR CLKR MRST ADSR CNTENR CNTRSTR CNT/MSKR A8R A9R A10R A11R A12R VSS VDD A13R
DQ8L DQ7L DQ6L DQ5L DQ4L VDD VSS DQ3L DQ2L DQ1L DQ0L DQ0R
Selection Guide
CY7C0853V CY7C0851V CY7C0852V CY7C0853V[6] -150 fMAX Max. Access Time (Clock to Data) Typical Operating Current ICC Typical Standby Current for ISB3 (Both Ports CMOS Level)[5]
Notes: 4. NC for CY7C0831V. 5. Not applicable for CY7C0853V. 6. For CY7C0853V all 150 MHz values are advance information.
VDD DQ4R DQ5R DQ6R DQ7R DQ8R A17R[3] A16R A15R A14R
A14L A15L A16L A17L[3]
DQ1R DQ2R DQ3R VSS
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
CY7C0853V CY7C0851V CY7C0852V CY7C0853V -133 133 4.4 270 10
CY7C0853V CY7C0851V CY7C0852V CY7C0853V -100 100 5 200 10
Unit MHz ns mA mA
150 4.0 300 10
Document #: 38-06059 Rev. *C
Page 6 of 33
CY7C0851V/CY7C0852V/CY7C0853V PRELIMINARY
Pin Definitions
Left Port A0L-A16L[1] ADSL Right Port A0R-A16R[1] ADSR Address Inputs. Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW for the part using the externally supplied address on the address pins and for loading this address into the burst address counter. Active LOW Chip Enable Input.[2] Active HIGH Chip Enable Input.[2] Clock Signal. Maximum clock input rate is fMAX. Counter Enable Input.[2] Asserting this signal LOW increments the burst address counter of its respective port on each rising edge of CLK. The increment is disabled if ADS or CNTRST are asserted LOW. Counter Reset Input.[2] Asserting this signal LOW resets to zero the unmasked portion of the burst address counter of its respective port. CNTRST is not disabled by asserting ADS or CNTEN. Address Counter Mask Register Enable Input.[2] Asserting this signal LOW enables access to the mask register. When tied HIGH, the mask register is not accessible and the address counter operations are enabled based on the status of the counter control signals. Output Enable Input. This asynchronous signal must be asserted LOW to enable the DQ data pins during Read operations. Mailbox Interrupt Flag Output. The mailbox permits communications between ports. The upper two memory locations can be used for message passing. INTL is asserted LOW when the right port writes to the mailbox location of the left port, and vice versa. An interrupt to a port is deasserted HIGH when it reads the contents of its mailbox. Counter Interrupt Output.[2] This pin is asserted LOW when the unmasked portion of the counter is incremented to all "1s." Read/Write Enable Input. Assert this pin LOW to write to, or HIGH to Read from the dual port memory array. Byte Select Inputs. Asserting these signals enables Read and Write operations to the corresponding bytes of the memory array. Master Reset Input. MRST is an asynchronous input signal and affects both ports. Asserting MRST LOW performs all of the reset functions as described in the text. A MRST operation is required at power-up. JTAG Test Mode Select Input. It controls the advance of JTAG TAP state machine. State machine transitions occur on the rising edge of TCK. JTAG Test Data Input. Data on the TDI input will be shifted serially into selected registers. JTAG Test Clock Input. JTAG Test Data Output. TDO transitions occur on the falling edge of TCK. TDO is normally three-stated except when captured data is shifted out of the JTAG TAP. Ground Inputs. Power Inputs. Description
CY7C0831V/CY7C0832V
CE0L CE1L CLKL CNTENL
CE0R CE1R CLKR CNTENR
CNTRSTL
CNTRSTR
CNT/MSKL
CNT/MSKR
DQ0L-DQ35L[1] OEL INTL
DQ0R-DQ35R[1] Data Bus Input/Output. OER INTR
CNTINTL R/WL B0L-B3L MRST
CNTINTR R/WR B0R-B3R
TMS TDI TCK TDO VSS VDD
Document #: 38-06059 Rev. *C
Page 7 of 33
CY7C0851V/CY7C0852V/CY7C0853V PRELIMINARY
Master Reset
The CY7C0831V undergoes a complete reset by taking its MRST input LOW. The MRST input can switch asynchronously to the clocks. An MRST initializes the internal burst counters to zero, and the counter mask registers to all ones (completely unmasked). MRST also forces the Mailbox Interrupt (INT) flags and the Counter Interrupt (CNTINT) flags HIGH. MRST must be performed on the CY7C0831V after power-up.
CY7C0831V/CY7C0832V
Mailbox Interrupts
The upper two memory locations may be used for message passing and permit communications between ports. Table 2 shows the interrupt operation for both ports. The highest memory location, 1FFFF is the mailbox for the right port and 1FFFE is the mailbox for the left port. Table 2 shows that in
order to set the INTR flag, a Write operation by the left port to address 1FFFF will assert INTR LOW. At least one byte has to be active for a Write to generate an interrupt. A valid Read of the 1FFFF location by the right port will reset INTR HIGH. At least one byte has to be active in order for a Read to reset the interrupt. When one port Writes to the other port's mailbox, the INT of the port that the mailbox belongs to is asserted LOW. The INT is reset when the owner (port) of the mailbox Reads the contents of the mailbox. The interrupt flag is set in a flow-thru mode (i.e., it follows the clock edge of the writing port). Also, the flag is reset in a flow-thru mode (i.e., it follows the clock edge of the reading port). Each port can read the other port's mailbox without resetting the interrupt. And each port can write to its own mailbox without setting the interrupt. If an application does not require message passing, INT pins should be left open.
Table 1. Address Counter and Counter-Mask Register Control Operation (Any Port)[2, 7, 8] CLK X MRST L H H H H H H H H H CNT/MSK X H H H H H L L L L CNTRST X L H H H H L H H H ADS X X L L H H X L L H CNTEN X X L H L H X L H X Operation Master Reset Counter Reset Counter Load Counter Readback Description Reset address counter to all 0s and mask register to all 1s. Reset counter unmasked portion to all 0s. Load counter with external address value presented on address lines. Read out counter internal value on address lines.
Counter Increment Internally increment address counter value. Counter Hold Mask Reset Mask Load Mask Readback Reserved Constantly hold the address value for multiple clock cycles. Reset mask register to all 1s. Load mask register with value presented on the address lines. Read out mask register value on address lines. Operation undefined
Table 2. Interrupt Operation Example [1, 9, 10, 11] Left Port Function Set Right INTR Flag Reset Right INTR Flag Set Left INTL Flag Reset Left INTL Flag R/WL L X X H CEL L X X L A0L-16L 1FFFF X X 1FFFE INTL X X L H R/WR X H L X CER X L L X Right Port A0R-16R X 1FFFF 1FFFE X INTR L H X X
Notes: 7. "X" = "Don't Care," "H" = HIGH, "L" = LOW. 8. Counter operation and mask register operation is independent of chip enables. 9. CE is internal signal. CE = LOW if CE0 = LOW and CE1 = HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of the CLK and can be deasserted after that. Data will be out after the following CLK edge and will be three-stated after the next CLK edge. 10. OE is "Don't Care" for mailbox operation. 11. At least one of B0, B1, B2, or B3 must be LOW.
Document #: 38-06059 Rev. *C
Page 8 of 33
CY7C0851V/CY7C0852V/CY7C0853V PRELIMINARY
Address Counter and Mask Register Operations [2, 12]
Each port of the CY7C085XV/CY7C083XV has a programmable burst address counter. The burst counter contains three 17-bit registers: a counter register, a mask register, and a mirror register. The counter register contains the address used to access the RAM array. It is changed only by the Counter Load, Increment, Counter Reset, and by master reset (MRST) operations. The mask register value affects the Increment and Counter Reset operations by preventing the corresponding bits of the counter register from changing. It also affects the counter interrupt output (CNTINT). The mask register is changed only by the Mask Load and Mask Reset operations, and by the MRST. The mask register defines the counting range of the counter register. It divides the counter register into two regions: zero or more "0s" in the most significant bits define the masked region, one or more "1s" in the least significant bits define the unmasked region. Bit 0 may also be "0," masking the least significant counter bit and causing the counter to increment by two instead of one. The mirror register is used to reload the counter register on increment operations (see "retransmit," below). It always contains the value last loaded into the counter register, and is changed only by the Counter Load, and Counter Reset operations, and by the MRST. Table 1 summarizes the operation of these registers and the required input control signals. The MRST control signal is asynchronous. All the other control signals in Table 1 (CNT/MSK, CNTRST, ADS, CNTEN) are synchronized to the port's CLK. All these counter and mask operations are independent of the port's chip enable inputs (CE0 and CE1). Counter Load Operation The address counter and mirror registers are both loaded with the address value presented at the address lines. This value ranges from 0 to 1FFFF. Mask Load Operation The mask register is loaded with the address value presented at the address lines. This value ranges from 0 to 1FFFF, although not all values permit correct increment operations. Permitted values are of the form 2n - 1 or 2n - 2. From the most significant bit to the least significant bit, permitted values have zero or more "0s," one or more "1s," or one "0." Thus 1FFFF, 003FE, and 00001 are permitted values, but 1F0FF, 003FC, and 00000 are not. Counter Readback Operation The internal value of the counter register can be read out on the address lines. Readback is pipelined; the address will be valid tCA2 after the next rising edge of the port's clock. If address readback occurs while the port is enabled (CE0 LOW and CE1 HIGH), the data lines (DQs) will be three-stated. Figure 1 shows a block diagram of the operation.
CY7C0831V/CY7C0832V
Mask Readback Operation The internal value of the mask register can be read out on the address lines. Readback is pipelined; the address will be valid tCM2 after the next rising edge of the port's clock. If mask readback occurs while the port is enabled (CE0 LOW and CE1 HIGH), the data lines (DQs) will be three-stated. Figure 1 shows a block diagram of the operation. Mask Reset Operation The mask register is reset to all "1s," which unmasks every bit of the counter. Master reset (MRST) also resets the mask register to all "1s." Counter Reset Operation All unmasked bits of the counter and mirror registers are reset to "0." All masked bits remain unchanged. A Mask Reset followed by a Counter Reset will reset the counter and mirror registers to 00000, as will master reset (MRST). Increment Operation Once the address counter register is initially loaded with an external address, the counter can internally increment the address value, potentially addressing the entire memory array. Only the unmasked bits of the counter register are incremented. The corresponding bit in the mask register must be a "1" for a counter bit to change. The counter register is incremented by 1 if the least significant bit is unmasked, and by 2 if it is masked. If all unmasked bits are "1," the next increment will wrap the counter back to the initially loaded value. If an Increment results in all the unmasked bits of the counter being "1s," a counter interrupt flag (CNTINT) is asserted. The next Increment will return the counter register to its initial value, which was stored in the mirror register. The counter address can instead be forced to loop to 00000 by externally connecting CNTINT to CNTRST.[13] An increment that results in one or more of the unmasked bits of the counter being "0" will de-assert the counter interrupt flag. The example in Figure 2 shows the counter mask register loaded with a mask value of 0003Fh unmasking the first 6 bits with bit "0" as the LSB and bit "16" as the MSB. The maximum value the mask register can be loaded with is 1FFFFh. Setting the mask register to this value allows the counter to access the entire memory space. The address counter is then loaded with an initial value of 8h. The base address bits (in this case, the 6th address through the 16th address) are loaded with an address value but do not increment once the counter is configured for increment operation. The counter address will start at address 8h. The counter will increment its internal address value till it reaches the mask register value of 3Fh. The counter wraps around the memory block to location 8h at the next count. CNTINT is issued when the counter reaches its maximum value. Hold Operation The value of all three registers can be constantly maintained unchanged for an unlimited number of clock cycles. Such operation is useful in applications where wait states are needed, or when address is available a few cycles ahead of data in a shared bus interface.
Notes: 12. This section describes the CY7C0852V and CY7C0831V, which have 17 address bits and a maximum address value of 1FFFF. The CY7C0832V has 18 address bits, register lengths of 18 bits, and a maximum address value of 3FFFF. The CY7C0851V has 16 address bits, register lengths of 16 bits, and a maximum address value of FFFF. 13. CNTINT and CNTRST specs are guaranteed by design to operate properly at speed grade operating frequency when tied together.
Document #: 38-06059 Rev. *C
Page 9 of 33
CY7C0851V/CY7C0852V/CY7C0853V PRELIMINARY
Counter Interrupt The counter interrupt (CNTINT) is asserted LOW when an increment operation results in the unmasked portion of the counter register being all "1s." It is deasserted HIGH when an Increment operation results in any other value. It is also de-asserted by Counter Reset, Counter Load, Mask Reset and Mask Load operations, and by MRST. Retransmit Retransmit is a feature that allows the Read of a block of memory more than once without the need to reload the initial address. This eliminates the need for external logic to store and route data. It also reduces the complexity of the system design and saves board space. An internal "mirror register" is used to store the initially loaded address counter value. When
CY7C0831V/CY7C0832V
the counter unmasked portion reaches its maximum value set by the mask register, it wraps back to the initial value stored in this "mirror register." If the counter is continuously configured in increment mode, it increments again to its maximum value and wraps back to the value initially stored into the "mirror register." Thus, the repeated access of the same data is allowed without the need for any external logic. Counting by Two When the least significant bit of the mask register is "0," the counter increments by two. This may be used to connect the CY7C0851V/CY7C0852V as a 72-bit single port SRAM in which the counter of one port counts even addresses and the counter of the other port counts odd addresses. This even-odd address scheme stores one half of the 72-bit data in even memory locations, and the other half in odd memory locations.
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CY7C0851V/CY7C0852V/CY7C0853V PRELIMINARY CY7C0831V/CY7C0832V
CNT/MSK CNTEN ADS CNTRST MRST Decode Logic
Bidirectional Address Lines
Mask Register Counter/ Address Register
Address Decode
RAM Array
CLK
From Address Lines
17 Mirror
Load/Increment Counter
1 1 0 0
To Readback and Address Decode
From Mask Register
17 Increment Logic Wrap
17
From Mask From Counter
17 17 +1 1 +2 0
17 Bit 0 Wrap Detect Wrap
1 0
17
To Counter
Figure 1. Counter, Mask, and Mirror Logic Block Diagram[1]
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CY7C0851V/CY7C0852V/CY7C0853V PRELIMINARY
Example: Load Counter-Mask Register = 3F CNTINT H
CY7C0831V/CY7C0832V
0
0
0s
01
1
1
1
1
1 Mask Register bit-0
216 215 Masked Address Load Address Counter = 8 H XX 216 215 Max Address Register L XX 216 215 Max + 1 Address Register H XX 216 215 Xs Xs Xs
26 25 24 23 22 21 20 Unmasked Address X0 0 1 0 0 0
26 25 24 23 22 21 20 X11 1 1 1 1
Address Counter bit-0
26 25 24 23 22 21 20 X0 0 1 00 0
26 25 24 23 22 21 20
Figure 2. Programmable Counter-Mask Register Operation[1, 14]
IEEE 1149.1 Serial Boundary Scan (JTAG) [15]
The CY7C0851V/CY7C0852V/CY7C0853V incorporates an IEEE 1149.1 serial boundary scan test access port (TAP). The TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1-compliant TAPs. The TAP operates using JEDEC standard 3.3V I/O logic levels. It is composed of three input connections and one output connection required by the test logic defined by the standard. Disabling the JTAG Feature It is possible to operate the CY7C0851V/CY7C0852V/ CY7C0853V without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternatively be connected to VDD through a pull-up resistor. TDO should be left unconnected. Test Access Port-Test Clock (TCK) The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test Mode Select (TMS) The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this pin unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI) The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the MSB on any register. Test Data Out (TDO) The TDO output pin is used to serially clock data out from the registers. The output is active depending upon the current state of the TAP state machine (see TAP Controller State Diagram [FSM]). The output changes on the falling edge of TCK. TDO is connected to the LSB of any register. Performing a TAP Reset A reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This reset does not affect the operation of the CY7C0851V/CY7C0852V/CY7C0853V, and may be performed while the device is operating. An MRST must be performed on the CY7C0851V/CY7C0852V/CY7C0853V after power-up. Performing a Pause/Restart When a SHIFT-DR PAUSE-DR SHIFT-DR is performed the scan chain will output the next bit in the chain twice. For example, if the value expected from the chain is 1010101, the device will output a 11010101. This extra bit will cause some testers to report an erroneous failure for the CY7C0851/CY7C0852/CY7C0853 in a scan test. Therefore the tester should be configured to never enter the PAUSE-DR state.
Notes: 14. The "X" in this diagram represents the counter upper bits. 15. Boundary scan is IEEE 1149.1-compatible. See "Performing a Pause/Restart" for deviation from strict 1149.1 compliance.
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CY7C0851V/CY7C0852V/CY7C0853V PRELIMINARY
TAP Registers Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the CY7C0851V/CY7C0852V/CY7C0853V test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK. Instruction Register (IR) Four-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins as shown in Figure 4, the JTAG/BIST Controller Block Diagram. On power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state, as described in the previous section. When the TAP controller is in the CaptureIR state, the two least significant bits are loaded with a binary "01" pattern to allow for fault isolation of the board level serial test path. Bypass Register (BYR) To save time when serially shifting data through registers, it is sometimes advantageous to skip certain devices. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This allows data to be shifted through the CY7C0851V/CY7C0852V/CY7C0853V with minimal delay. The bypass register is set to "0" on the rising edge of TCK following entry into the Capture-DR state, if the current instruction causes the bypass register to be in the serial path between TDI and TDO. Boundary Scan Register (BSR) The boundary scan register is connected to all the input and output pins on the CY7C0851V/CY7C0852V/CY7C0853V, except the MRST pin. The boundary scan register is loaded with the contents of the CY7C0851V/CY7C0852V/ CY7C0853V input and output ring when the TAP controller is in the Capture-DR state. It is then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The EXTEST and SAMPLE/PRELOAD instructions can be used to capture the contents of the input and output ring. Identification Register (IDR) The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is in the instruction register. The IDCODE is hardwired into the CY7C0851V/CY7C0852V/CY7C0853V and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table. TAP Instruction Set Sixteen different instructions are possible with the four-bit instruction register. All combinations are listed in Table 5. Other code combinations are listed as RESERVED and should not be used. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins.
CY7C0831V/CY7C0832V
To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. EXTEST EXTEST is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. EXTEST allows circuitry external to the CY7C0851V/ CY7C0852V/CY7C0853V package to be tested. Boundaryscan register cells at output pins are used to apply test stimuli, while those at input pins capture test results. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO pins and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register on power-up or whenever the TAP controller is given a test logic reset state. The IDCODE value for the CY7C0851V is 0C001069h. The IDCODE value for the CY7C0852V is 0C002069h. The IDCODE value for the CY7C0853V is 0C002069h. High-Z The High-Z instruction causes the bypass register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. It also places all CY7C0851V/ CY7C0852V/CY7C0853V outputs into a High-Z state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions loaded into the instruction register and the TAP controller in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 10 MHz, while the CY7C0851V/CY7C0852V/CY7C0853V clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To guarantee that the boundary scan register will capture the correct value of a signal, the CY7C0851V/CY7C0852V/ CY7C0853V signal must be stabilized long enough to meet the TAP controller's capture set-up plus hold times. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. If the TAP controller goes into the Update-DR state, the sampled data will be updated. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected on a board.
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CY7C0851V/CY7C0852V/CY7C0853V PRELIMINARY
CLAMP The optional CLAMP instruction allows the state of the signals driven from CY7C0851V/CY7C0852V/CY7C0853V pins to be determined from the boundary-scan register while the BYPASS register is selected as the serial path between TDI and TDO. CLAMP controls boundary cells to 1 or 0. NBSRST This is the Non-Boundary Scan Reset instruction. NBSRST places the Bypass Register (BYR) between TDI and TDO when selected. Its function is to reset every logic (similar to MRST) except that it does not reset the JTAG logic. Boundary Scan Cells (BSC) Every CY7C0851V/CY7C0852V/CY7C0853V output has two boundary scan cells; one for data, and one for three-state 1 TEST-LOGIC RESET 0 0 RUN_TEST/ IDLE 1 SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT-DR 1 EXIT1-DR 0 PAUSE-DR 1 0 EXIT2-DR 1 UPDATE-DR 1 0 0 0 1 0 1 CAPTURE-IR 0 SHIFT-IR 1 EXIT1-IR 0 PAUSE-IR 1 EXIT2-IR 1 UPDATE-IR 1 0 0 1 0 1 1 SELECT IR-SCAN 0
CY7C0831V/CY7C0832V
control. JTAG TAP pins (TDI, TMS, TDO, TCK), MRST, and all power and ground pins have no scan cell. Other CY7C0851V/CY7C0852V/CY7C0853V inputs have only the data scan cell. Active and Standby Supply Current[17] When the instruction in the JTAG instruction register selects the Boundary Scan Register (BSR) and the TAP controller is in any state except TEST-LOGIC-RESET or RUN-TEST/IDLE, then the device supply current (ICC or ISB1/2/3/4) will increase. With the JTAG logic in this state, and both ports inactive with CMOS input levels, it is possible for the supply current to exceed the ISB3 value given in the Electrical Characteristics section of this datasheet.
Figure 3. TAP Controller State Diagram (FSM)[16]
Notes: 16. The "0"/"1" next to each state represents the value at TMS at the rising edge of CLK. 17. ISB3 values only if JTAG pins are not active and mpdaster reset (MRST) not enabled.
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CY7C0851V/CY7C0852V/CY7C0853V PRELIMINARY CY7C0831V/CY7C0832V
0 Bypass Register (BYR)
3
2
1
0
Instruction Register (IR)
TDI 31 30 29 0
Selection Circuitry
TDO
Identification Register (IDR)
(MUX)
n-1
0 Boundary Scan Register (BSR)
TCK TMS MRST
TAP CONTROLLER
Figure 4. JTAG TAP Controller Block Diagram Table 3. Identification Register Definitions Instruction Field Revision Number (31:28) Cypress Device ID
[18]
Value 0h C002h 034h 1
Description Reserved for version number. Defines Cypress part number for CY7C0852V. Allows unique identification of CY7C0851V/CY7C0852V/ CY7C0853V vendor. Indicates the presence of an ID register.
(27:12)
Cypress JEDEC ID (11:1) ID Register Presence (0) Table 4. Scan Registers Sizes
Register Name Instruction Bypass Identification Boundary Scan
Note: 18. Cypress Device ID is C001h for Cypress part CY7C0851V.
Bit Size 4 1 32 n
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CY7C0851V/CY7C0852V/CY7C0853V PRELIMINARY
Table 5. Instruction Identification Codes Instruction EXTEST BYPASS IDCODE HIGHZ CLAMP SAMPLE/PRELOAD NBSRST RESERVED 0000 1111 1011 0111 0100 1000 1100 All other codes Code Description Captures the Input/Output ring contents. Places the BSR between the TDI and TDO. Places the BYR between TDI and TDO. Loads the IDR with the vendor ID code and places the register between TDI and TDO. Places BYR between TDI and TDO. Forces all CY7C0851V/CY7C0852V/ CY7C0853V output drivers to a High-Z state. Controls boundary to 1/0. Places BYR between TDI and TDO. Captures the input/output ring contents. Places BSR between TDI and TDO. Resets the non-boundary scan logic. Places BYR between TDI and TDO. Other combinations are reserved. Do not use other than the above.
CY7C0831V/CY7C0832V
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CY7C0851V/CY7C0852V/CY7C0853V PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................ -65C to + 150C Ambient Temperature with Power Applied............................................-55C to + 125C Supply Voltage to Ground Potential .............. -0.5V to + 4.6V DC Voltage Applied to Outputs in High-Z State .........................-0.5V to VDD + 0.5V
CY7C0831V/CY7C0832V
DC Input Voltage .............................. -0.5V to VDD + 0.5V[19] Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage .......................................... > 2000V (JEDEC JESD22-A114-2000B) Latch-up Current..................................................... > 200 mA
Operating Range
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VDD 3.3V 165 mV 3.3V 165 mV
Electrical Characteristics Over the Operating Range
CY7C0851V/CY7C0852V/CY7C0853V[6] CY7C0831V/CY7C0832V -150 Parameter VOH VOL VIH VIL IOZ IIX1 IIX2 ICC ISB1[5] ISB2[5] ISB3[17,5] ISB4[5] Description Output LOW Voltage (VDD = Min., IOL= +4.0 mA) Input HIGH Voltage Input LOW Voltage Output Leakage Current Input Leakage Current Except TDI, TMS, MRST Input Leakage Current TDI, TMS, MRST Operating Current (VDD = Max., IOUT = 0 mA) Outputs Disabled Standby Current (Both Ports TTL Level) CEL and CER VIH, f = fMAX Standby Current (One Port TTL Level) CEL | CER VIH, f = fMAX Standby Current (Both Ports CMOS Level) CEL and CER VDD - 0.2V, f = 0 Standby Current (One Port CMOS Level) CEL | CER VIH, f = fMAX Com'l. Indust. Com'l. Indust. Com'l. Indust. Com'l. Indust. Com'l. Indust. 200 255 180 230 130 175 10 75 10 75 10 75 230 280 220 250 145 190 40 120 35 115 25 110 -10 -10 -0.1 300 2.0 0.8 10 10 1.0 450 -10 -10 -0.1 270 Output HIGH Voltage (VDD = Min., IOH= -4.0 mA) 2.4 0.4 2.0 0.8 10 10 1.0 400 -10 -10 -0.1 200 2.4 0.4 2.0 0.8 10 10 1.0 310 -133 2.4 0.4 -100 V V V V A A mA mA mA mA mA mA mA mA mA mA mA Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
Shaded areas contain advance information.
Capacitance
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VDD = 3.3V Max. (all) 13 10 Max. (CY7C0853) 22 20 Unit pF pF
Notes: 19. Pulse width < 20 ns. 20. (Internal I/O pad Capacitance = 10 pF) + AC Test Load. 21. External AC Test Load Capacitance = 10 pF. 22. Except JTAG signals (tr and tf < 10 ns [max.]).
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CY7C0851V/CY7C0852V/CY7C0853V PRELIMINARY
AC Test Load and Waveforms
3.3V Z0 = 50 OUTPUT C = 10 pF VTH = 1.5V OUTPUT C = 5 pF R2 = 435 R = 50 R1 = 590
CY7C0831V/CY7C0832V
(a) Normal Load (Load 1)
(b) Three-state Delay (Load 2)
3.0V 90% ALL INPUT PULSES Vss < 2 ns 10% 90% 10% < 2 ns
Switching Characteristics Over the Operating Range
CY7C0851V/CY7C0852V/CY7C0853V[6] CY7C0831V/CY7C0832V -150 Parameter fMAX2 tCYC2 tCH2 tCL2 tR tF tSA tHA tSB tHB tSC tHC tSW tHW tSD tHD tSAD tHAD tSCN tHCN tSRST tHRST tSCM tHCM Clock Cycle Time Clock HIGH Time Clock LOW Time Clock Rise Time Clock Fall Time Address Set-Up Time Address Hold Time Byte Select Set-Up Time Byte Select Hold Time Chip Enable Set-Up Time Chip Enable Hold Time R/W Set-Up Time R/W Hold Time Input Data Set-Up Time Input Data Hold Time ADS Set-Up Time ADS Hold Time CNTEN Set-Up Time CNTEN Hold Time CNTRST Set-Up Time CNTRST Hold Time CNT/MSK Set-Up Time CNT/MSK Hold Time 2.3 0.6 2.3 0.6 2.3 0.6 2.3 0.6 2.3 0.6 2.3 0.6 2.3 0.6 2.3 0.6 2.3 0.6 Description Maximum Operating Frequency 6.7 2.7 2.7 2.0 2.0 2.5 0.6 2.5 0.6 2.5 0.6 2.5 0.6 2.5 0.6 2.5 0.6 2.5 0.6 2.5 0.6 2.5 0.6 Min. Max. 150 7.5 3.0 3.0 2.0 2.0 3.0 0.5 3.0 0.5 3.0 0.5 3.0 0.5 3.0 0.5 3.0 0.5 3.0 0.5 3.0 0.5 3.0 0.5 -133 Min. Max. 133 10 4.0 4.0 3.0 3.0 -100 Min. Max. 100 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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CY7C0851V/CY7C0852V/CY7C0853V PRELIMINARY
Switching Characteristics Over the Operating Range (continued)
CY7C0851V/CY7C0852V/CY7C0853V[6] CY7C0831V/CY7C0832V -150 Parameter tOE tOLZ[23, 24] tOHZ[23, 24] tCD2 tCA2 tCM2 tDC tCKHZ tSINT tRINT tSCINT tRCINT tCCS tRS tRSS tRSR tRSF tRSCNTINT
[23, 24]
CY7C0831V/CY7C0832V
-133 Min. 0 4.0 4.0 4.0 4.0 0 4.4 4.4 4.4 4.4 1.0 4.0 4.0 6.7 6.7 5.0 5.0 0 1.0 0.5 0.5 0.5 0.5 6.0 7.5 6.0 7.5 6.0 5.8 6.5 7.0 4.4 4.4 7.5 7.5 5.7 5.7 1.0 0 1.0 0.5 0.5 0.5 0.5 8.0 10 8.5 10 Max. 4.4 0 0 4.0
-100 Min. Max. 5.0 5.0 5.0 5.0 5.0 5.0 5.0 10 10 7.5 7.5 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 8.0 8.0 ns ns
Description Output Enable to Data Valid OE to Low Z OE to High Z Clock to Data Valid Clock to Counter Address Valid Clock to Mask Register Readback Valid Data Output Hold After Clock HIGH Clock HIGH to Output High Z Clock HIGH to Output Low Z Clock to INT Set Time Clock to INT Reset Time Clock to CNTINT Set Time Clock to CNTINT Reset time Clock to Clock Skew Master Reset Pulse Width Master Reset Set-Up Time Master Reset Recovery Time Master Reset to Outputs Inactive Master Reset to Counter Interrupt Flag Reset Time
Min. 0 0
Max.
1.0 0 1.0 0.5 0.5 0.5 0.5 5.2 7.0 6.0 6.0
tCKLZ[23, 24]
Port to Port Delays Master Reset Timing
JTAG Timing and Switching Waveforms
CY7C0852V -150/133/100 Parameter fJTAG tTCYC tTH tTL tTMSS tTMSH tTDIS tTDIH tTDOV tTDOX TCK Clock Cycle Time TCK Clock HIGH Time TCK Clock LOW Time TMS Set-Up to TCK Clock Rise TMS Hold After TCK Clock Rise TDI Set-Up to TCK Clock Rise TDI Hold after TCK Clock Rise TCK Clock LOW to TDO Valid TCK Clock LOW to TDO Invalid 0 Description Maximum JTAG TAP Controller Frequency 100 40 40 10 10 10 10 30 Min. Max. 10 Unit MHz ns ns ns ns ns ns ns ns ns
Notes: 23. This parameter is guaranteed by design, but it is not production tested. 24. Test conditions used are Load 2.
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CY7C0851V/CY7C0852V/CY7C0853V PRELIMINARY
tTH tTL
CY7C0831V/CY7C0832V
Test Clock TCK Test Mode Select TMS
tTMSS
tTCYC tTMSH
tTDIS Test Data-In TDI Test Data-Out TDO
tTDIH
tTDOX
tTDOV
Switching Waveforms
Master Reset
MRST ALL ADDRESS/ DATA LINES ALL OTHER INPUTS TMS CNTINT INT TDO tRSF tRSS tRSR ACTIVE tRS
INACTIVE
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CY7C0851V/CY7C0852V/CY7C0853V PRELIMINARY
Switching Waveforms (continued)
Read Cycle[25, 26, 27, 28, 9]
tCH2 CLK tCYC2 tCL2
CY7C0831V/CY7C0832V
CE tSC tSB B0-B3 tHC tHB tSC tHC
R/W tSW tSA ADDRESS DATAOUT An 1 Latency tHW tHA An+1 tCD2 Qn tCKLZ OE
tOE Notes: 25. OE is asynchronously controlled; all other inputs (excluding MRST and JTAG) are synchronous to the rising clock edge. 26. ADS = CNTEN = LOW, and MRST = CNTRST = CNT/MSK = HIGH. 27. The output is disabled (high-impedance state) by CE = VIH following the next rising edge of the clock. 28. Addresses do not have to be accessed sequentially since ADS = CNTEN = VIL with CNT/MSK = VIH constantly loads the address on the rising edge of the CLK. Numbers are for reference only.
An+2 tDC Qn+1 tOHZ
An+3
Qn+2 tOLZ
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CY7C0851V/CY7C0852V/CY7C0853V PRELIMINARY
Switching Waveforms (continued)
Bank Select Read[29, 30]
tCH2 CLK tSA ADDRESS(B1) tSC CE(B1) tCD2 DATAOUT(B1) tSA ADDRESS (B2) A0 tHA A1 tSC CE(B2) tSC DATAOUT(B2) tCKLZ tHC tCD2 Q2 tCKLZ tCKHZ tCD2 Q4 tSC Q0 tDC A2 tHC tHC tCD2 Q1 tDC A3 A4 tCKLZ A5 tCKHZ tCD2 Q3 tCKHZ A0 tHC tHA A1 A2 A3 A4 A5 tCYC2 tCL2
CY7C0831V/CY7C0832V
Read-to-Write-to-Read (OE = LOW)[28, 31, 32, 33, 34]
tCH2 CLK tCYC2 tCL2
CE tSC tHC
tSW R/W tSW ADDRESS tSA DATAIN An tHA tCD2 Qn tHW An+1 An+2
tHW
An+2 tSD tHD
An+3
An+4
tCKHZ
Dn+2
tCD2 Qn+3 tCKLZ
DATAOUT READ
NO OPERATION
WRITE
READ
Notes: 29. In this depth-expansion example, B1 represents Bank #1 and B2 is Bank #2; each bank consists of one Cypress CY7C085XV device from this data sheet. ADDRESS(B1) = ADDRESS(B2). 30. ADS = CNTEN= B0 - B3 = OE = LOW; MRST = CNTRST = CNT/MSK = HIGH. 31. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals. 32. During "No Operation," data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity. 33. CE0 = OE = B0 - B3 = LOW; CE1 = R/W = CNTRST = MRST = HIGH. 34. CE0 = B0 - B3 = R/W = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH. When R/W first switches low, since OE = LOW, the Write operation cannot be completed (labelled as no operation). One clock cycle is required to three-state the I/O for the Write operation on the next rising edge of CLK.
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CY7C0851V/CY7C0852V/CY7C0853V PRELIMINARY
Switching Waveforms (continued)
Read-to-Write-to-Read (OE Controlled)[28, 31, 33, 34]
tCH2 CLK tCYC2 tCL2
CY7C0831V/CY7C0832V
CE tSC tHC tSW tHW
R/W
tSW An
tHW An+1 tHA An+2 tSD tHD Dn+2 tCD2 Dn+3 tCD2 Qn tOHZ Qn+4 An+3 An+4 An+5
ADDRESS tSA DATAIN
DATAOUT
OE READ WRITE READ
[2, 33]
Read with Address Counter Advance
tCH2 CLK tSA ADDRESS tSAD ADS An tHAD tHA tCYC2 tCL2
tSAD CNTEN tSCN DATAOUT Qx-1 READ EXTERNAL ADDRESS tHCN Qx tDC READ WITH COUNTER tCD2 Qn tSCN Qn+1
tHAD
tHCN Qn+2 Qn+3
COUNTER HOLD
READ WITH COUNTER
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CY7C0851V/CY7C0852V/CY7C0853V PRELIMINARY
Switching Waveforms (continued)
Write with Address Counter Advance [2, 34]
tCH2 CLK tSA ADDRESS An tHA tCYC2 tCL2
CY7C0831V/CY7C0832V
INTERNAL ADDRESS tSAD ADS tHAD
An
An+1
An+2
An+3
An+4
CNTEN tSCN DATAIN tSD Dn tHD WRITE EXTERNAL ADDRESS tHCN Dn+1 WRITE WITH COUNTER Dn+1 Dn+2 Dn+3 Dn+4
WRITE COUNTER HOLD
WRITE WITH COUNTER
Document #: 38-06059 Rev. *C
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CY7C0851V/CY7C0852V/CY7C0853V PRELIMINARY
Switching Waveforms (continued)
Counter Reset [2, 35, 36]
tCYC2 tCH2 tCL2 CLK tSA ADDRESS INTERNAL ADDRESS An tHA Am Ap
CY7C0831V/CY7C0832V
Ax tSW tHW
0
1
An
Am
Ap
R/W
ADS
CNTEN tSRST tHRST CNTRST tSD tHD DATAIN D0 tCD2
[48] DATAOUT
tCD2 Q0 Q1 Qn
tCKLZ COUNTER RESET WRITE ADDRESS 0 READ ADDRESS 0 READ ADDRESS 1 READ ADDRESS An READ ADDRESS Am
Notes: 35. CE0 = B0 - B3 = LOW; CE1 = MRST = CNT/MSK = HIGH. 36. No dead cycle exists during counter reset. A Read or Write cycle may be coincidental with the counter reset.
Document #: 38-06059 Rev. *C
Page 25 of 33
CY7C0851V/CY7C0852V/CY7C0853V PRELIMINARY
Switching Waveforms (continued)
Readback State of Address Counter or Mask Register[2, 37, 38, 39, 40]
tCYC2 tCH2 tCL2 CLK tSA tHA EXTERNAL ADDRESS A0-A16 INTERNAL ADDRESS tSAD tHAD ADS tSCN tHCN CNTEN tCD2 DATAOUT Qx-2 Qx-1 tCKHZ Qn tCKLZ Qn+1 Qn+2 Qn+3 An tCA2 or tCM2 An*
CY7C0831V/CY7C0832V
An
An+1
An+2
An+3
An+4
LOAD EXTERNAL ADDRESS
READBACK COUNTER INTERNAL ADDRESS
INCREMENT
Notes: 37. CE0 = OE = B0 - B3 = LOW; CE1 = R/W = CNTRST = MRST = HIGH. 38. Address in output mode. Host must not be driving address bus after tCKLZ in next clock cycle. 39. Address in input mode. Host can drive address bus after tCKHZ. 40. An * is the internal value of the address counter (or the mask register depending on the CNT/MSK level) being Read out on the address lines.
Document #: 38-06059 Rev. *C
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CY7C0851V/CY7C0852V/CY7C0853V PRELIMINARY
Switching Waveforms (continued)
Left_Port (L_Port) Write to Right_Port (R_Port) Read[41, 42, 43]
tCH2 CLKL tSA L_PORT ADDRESS tSW R/WL tCKHZ tSD Dn tCCS An tHW tHA tCYC2 tCL2
CY7C0831V/CY7C0832V
tHD
L_PORT
DATAIN tCYC2 tCL2 tCH2
tCKLZ
CLKR
tSA R_PORT ADDRESS An
tHA
R/WR tCD2
R_PORT
DATAOUT tDC
Qn
Notes: 41. CE0 = OE = ADS = CNTEN = B0 - B3 = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH. 42. This timing is valid when one port is writing, and other port is reading the same location at the same time. If tCCS is violated, indeterminate data will be Read out. 43. If tCCS < minimum specified value, then R_Port will Read the most recent data (written by L_Port) only (2 * tCYC2 + tCD2) after the rising edge of R_Port's clock. If tCCS > minimum specified value, then R_Port will Read the most recent data (written by L_Port) (tCYC2 + tCD2) after the rising edge of R_Port's clock.
Document #: 38-06059 Rev. *C
Page 27 of 33
CY7C0851V/CY7C0852V/CY7C0853V PRELIMINARY
Switching Waveforms (continued)
Counter Interrupt and Retransmit[2, 44, 45, 46, 47, 48]
tCH2 CLK tCYC2 tCL2
CY7C0831V/CY7C0832V
tSCM
tHCM
CNT/MSK
ADS
CNTEN
COUNTER INTERNAL ADDRESS
1FFFC
1FFFD
1FFFE tSCINT
1FFFF tRCINT
Last_Loaded
Last_Loaded +1
CNTINT
Notes: 44. CE0 = OE = B0 - B3 = LOW; CE1 = R/W = CNTRST = MRST = HIGH. 45. CNTINT is always driven. 46. CNTINT goes LOW when the unmasked portion of the address counter is incremented to the maximum value. 47. The mask register assumed to have the value of 1FFFFh. 48. Retransmit happens if the counter remains in increment mode after it wraps to initially loaded value.
Document #: 38-06059 Rev. *C
Page 28 of 33
CY7C0851V/CY7C0852V/CY7C0853V PRELIMINARY
Switching Waveforms (continued)
MailBox Interrupt Timing[49, 50, 51, 52, 53]
tCH2 CLKL tSA L_PORT ADDRESS INTR tCYC2 tCL2 tHA An tSINT tRINT An+1 An+2 An+3 tCYC2 tCL2
CY7C0831V/CY7C0832V
1FFFF
tCH2 CLKR
tSA R_PORT ADDRESS Am
tHA Am+1 1FFFF Am+3 Am+4
Table 6. Read/Write and Enable Operation (Any Port)[1, 7, 54, 55, 56] Inputs OE X X X L H X CLK CE0 H X L L L CE1 X L H H H R/W X X L H X Outputs DQ0 - DQ35 High-Z High-Z DIN DOUT High-Z Deselected Deselected Write Read Outputs Disabled Operation
Notes: 49. CE0 = OE = ADS = CNTEN = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH. 50. Address "1FFFF" is the mailbox location for R_Port. 51. L_Port is configured for Write operation, and R_Port is configured for Read operation. 52. At least one byte enable (B0 - B3) is required to be active during interrupt operations. 53. Interrupt flag is set with respect to the rising edge of the Write clock, and is reset with respect to the rising edge of the Read clock. 54. OE is an asynchronous input signal. 55. When CE changes state, deselection and Read happen after one cycle of latency. 56. CE0 = OE = LOW; CE1 = R/W = HIGH.
Document #: 38-06059 Rev. *C
Page 29 of 33
CY7C0851V/CY7C0852V/CY7C0853V PRELIMINARY
Ordering Information
256K x 36 (9M) 3.3V Synchronous CY7C0853V Dual-Port SRAM Speed (MHz) 150 133 100 Ordering Code CY7C0853V-150BBC CY7C0853V-133BBC CY7C0853V-100BBC CY7C0853V-100BBI Speed (MHz) 150 133 100 Package Name BB172 BB172 BB172 BB172 Package Name A120 A120 A120 A120 BB172 A176 BB172 BB172 A176 BB172 A176 BB172 A176 Package Name A120 A120 A120 Package Name BB172 A176 BB172 A176 BB172 BB172 A176 Package Type Operating Range
CY7C0831V/CY7C0832V
172-ball Grid Array 15 mm x 15 mm with 1.0 mm pitch (BGA) Commercial 172-ball Grid Array 15 mm x 15 mm with 1.0 mm pitch (BGA) Commercial 172-ball Grid Array 15 mm x 15 mm with 1.0 mm pitch (BGA) Commercial 172-ball Grid Array 15 mm x 15 mm with 1.0 mm pitch (BGA) Industrial Operating Range Commercial Commercial Commercial Industrial
256K x 18 (4M) 3.3V Synchronous CY7C0832V Dual-Port SRAM Ordering Code CY7C0832V-150AC CY7C0832V-133AC CY7C0832V-100AC CY7C0832V-100AI 150 133 CY7C0852V-150BBC CY7C0852V-150AC CY7C0852V-133BBC CY7C0852V-133BBI CY7C0852V-133AC 100 CY7C0852V-100BBC CY7C0852V-100AC CY7C0852V-100BBI CY7C0852V-100AI Speed (MHz) 150 133 100 Speed (MHz) 150 133 Package Type 120-pin Flat Pack 14 mm x 14 mm (TQFP) 120-pin Flat Pack 14 mm x 14 mm (TQFP) 120-pin Flat Pack 14 mm x 14 mm (TQFP) 120-pin Flat Pack 14 mm x 14 mm (TQFP)
128K x 36 (4M) 3.3V Synchronous CY7C0852V Dual-Port SRAM 172-ball Grid Array 15 mm x 15 mm with 1.0 mm pitch (BGA) Commercial 176-pin Flat Pack 24 mm x 24 mm (TQFP) Commercial 172-ball Grid Array 15 mm x 15 mm with 1.0 mm pitch (BGA) Commercial 172-ball Grid Array 15 mm x 15 mm with 1.0 mm pitch (BGA) Industrial 176-pin Flat Pack 24 mm x 24 mm (TQFP) 176-pin Flat Pack 24 mm x 24 mm (TQFP) 176-pin Flat Pack 24 mm x 24 mm (TQFP) Commercial Commercial Industrial Operating Range Commercial Commercial Commercial Operating Range Commercial Commercial 172-ball Grid Array 15 mm x 15 mm with 1.0 mm pitch (BGA) Commercial 172-ball Grid Array 15 mm x 15 mm with 1.0 mm pitch (BGA) Industrial
128K x 18 (2M) 3.3V Synchronous CY7C0831V Dual-Port SRAM Ordering Code CY7C0831V-150AC CY7C0831V-133AC CY7C0831V-100AC Package Type 120-pin Flat Pack 14 mm x 14 mm (TQFP) 120-pin Flat Pack 14 mm x 14 mm (TQFP) 120-pin Flat Pack 14 mm x 14 mm (TQFP)
64K x 36 (2M) 3.3V Synchronous CY7C0851V Dual-Port SRAM Ordering Code CY7C0851V-150BBC CY7C0851V-150AC CY7C0851V-133BBC CY7C0851V-133AC CY7C0851V-133BBI 100 CY7C0851V-100BBC CY7C0851V-100AC
Shaded areas contain advance information.
Package Type 176-pin Flat Pack 24 mm x 24 mm (TQFP) 176-pin Flat Pack 24 mm x 24 mm (TQFP)
172-ball Grid Array 15 mm x 15 mm with 1.0 mm pitch (BGA) Commercial 172-ball Grid Array 15 mm x 15 mm with 1.0 mm pitch (BGA) Commercial 172-ball Grid Array 15 mm x 15 mm with 1.0 mm pitch (BGA) Industrial 172-ball Grid Array 15 mm x 15 mm with 1.0 mm pitch (BGA) Commercial 176-pin Flat Pack 24 mm x 24 mm (TQFP) Commercial
Document #: 38-06059 Rev. *C
Page 30 of 33
CY7C0851V/CY7C0852V/CY7C0853V PRELIMINARY
Package Diagrams
120-pin thin Quad Flatpack (14 x 14 x 1.4 mm) A120
CY7C0831V/CY7C0832V
51-85100
176-lead Thin Quad Flat Pack (24 x 24 x 1.4 mm) A176
51-85132
Document #: 38-06059 Rev. *C
Page 31 of 33
CY7C0851V/CY7C0852V/CY7C0853V PRELIMINARY
Package Diagrams (continued)
172-ball BGA BB172
CY7C0831V/CY7C0832V
51-85114-*A
FLEx36 is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-06059 Rev. *C
Page 32 of 33
(c) Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C0851V/CY7C0852V/CY7C0853V PRELIMINARY CY7C0831V/CY7C0832V
Document Title: CY7C0851V/CY7C0852V/CY7C0853V/CY7C0831V/CY7C0832V 3.3V 64K/128K/256K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM Document Number: 38-06059 REV. ** *A ECN NO. 111473 111942 Issue Date 11/27/01 12/21/01 Orig. of Change DSG JFU Description of Change Change from Spec number: 38-01056 to 38-06059 Updated capacitance values Updated switching parameters and ISB3 Updated "Read-to-Write-to-Read (OE Controlled)" waveform Revised static discharge voltage Revised footnote regarding ISB3 Updated Isb values Updated ESD voltage Corrected 0853 pins L3 and L12 Added discussion of Pause/Restart for JTAG boundary scan
*B
113741
04/02/02
KRE
*C
114704
04/24/02
KRE
Document #: 38-06059 Rev. *C
Page 33 of 33

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